Thermally-assisted switching magnetic tunnel junction (TAS-MTJ) based magnetic random access memory (MRAM) cells have been described in U.S. Pat. No. 6,950,335 and U.S. Patent Application Publication No. US 2006/0291276 A1 while single-line (SL) TAS-MTJ-based MRAM cells have been described in the co-pending U.S. patent application “SYSTEM AND METHOD FOR WRITING DATA TO MAGNETORESISTIVE RANDOM ACCESS MEMORY CELLS,” Ser. No. 12/418,747, filed Apr. 6, 2009, which is assigned to the assignee of the present application and the disclosure of which is hereby incorporated herein by reference in its entirety and for all purposes. These typical implementations use one dedicated conductor field line per bit line or per word line.
FIG. 1a shows an implementation of a conventional TAS-MTJ based MRAM cell 1. As illustrated in FIG. 1a, the cell 1 comprises a magnetic tunnel junction 2 formed from an insulating layer 22 disposed between a reference layer 23, having a fixed magnetization, and a storage layer 21, having a magnetization which direction is adjustable at a threshold temperature. The magnetic tunnel junction 2 is placed between a selection CMOS transistor 3 and a bit line 4, represented parallel to the page and connecting the magnetic tunnel junction 2. Also orthogonal with the bit line 4, a field line 5 is placed underneath the magnetic tunnel junction 2. This configuration includes a strap 7 between the bottom of the magnetic tunnel junction 2 and the selection transistor 3.
The writing of the TAS-MTJ-based MRAM cell 1 is performed by heating the magnetic tunnel junction 2 with a heating current 31 that passes through the magnetic tunnel junction 2 via the bit line 4. This is achieved when the transistor 3 is in a conducting mode (ON). Simultaneously (or after a short time delay) and once the magnetic tunnel junction 2 has reached the suitable temperature threshold, a field current 51 is passed through the field line 5, producing a magnetic field 52 capable of addressing the magnetic tunnel junction 2 by switching the magnetization of the storage layer 21, into the appropriate direction. The heating current 31 then is turned off by setting the selection transistor 3 in a cutoff mode (OFF) or by removing the transistor's source-drain bias. The field current 51 is maintained during the cooling of the magnetic tunnel junction 2 and switched off when the magnetic tunnel junction 2 has reached a predetermined temperature, wherein the magnetization of the storage layer is frozen in the written state.
FIG. 1b illustrates a SL-TAS-MTJ-based MRAM cell 10, where the magnetic tunnel junction 2 is disposed between the selection transistor 3 and the field line 5. The field line 5 is shown as being electrically connected to the magnetic tunnel junction 2 on the side of the storage layer (not shown in FIG. 1b). A control current line (not shown) can be used to control the opening and the closing of the transistor 3 in order to address the SL-TAS-MTJ-based MRAM cell 10 individually. The field line 5 of the SL-TAS-MTJ-based MRAM cell 10 can fulfill several MRAM operational functions. First, the field line 5 can fulfill a function of a bit line by passing the heating current 31. The field line 5 likewise can fulfill a function of a field line by passing the field current 51 to produce the magnetic field 52 capable of switching the magnetization of the storage layer in the magnetic tunnel junction 2.
FIG. 2a represents two adjacent TAS-MTJ-based MRAM cells 1 and FIG. 2b represents two adjacent SL-TAS-MTJ-based MRAM cells 10. As shown in FIGS. 2a and 2b, each adjacent TAS-MTJ-based MRAM or SL-TAS-MTJ-based MRAM cell are addressed by a separate field line 5.
A magnetic memory device (not shown) can be formed by assembling an array comprising a plurality of the TAS-MTJ-based MRAM cell 1 or SL-TAS-MTJ-based MRAM cell 10. The array of cells 1, 10 can be disposed within a device package (not shown). When forming the magnetic memory device, the magnetic tunnel junction 2 can be connected on the side of the storage layer 21 to the bit line 4 and on the opposite side to the field line 5, in the case of the TAS-MTJ-based MRAM cell 1. The magnetic tunnel junction 2 is connected on the side of the storage layer 21 to the field line 5, in the case of the SL-TAS-MTJ-based MRAM cell 10. In the case of the TAS-MTJ-based MRAM cell 1, the field line 5 is preferably placed perpendicularly with reference to the bit line 4.
The magnetic memory device usually comprises a current driver (not represented) placed at each extremities of the field line 5 to control the direction of the field current 51. The current driver comprises two or more control transistors (not shown) depending on their configuration. In order to generate a magnetic field 52 able to switch the magnetization of the storage layer 21 in all the magnetic tunnel junctions 2 along the field line 5, the intensity of the field current 51 must be in the order of 10 mA or more. Consequently, current drivers having a large size must be used increasing the surface area of the memory cell array. Since the thickness of the field line 5 cannot be easily increased due to fabrication process limitations, the width of the field line 5 is restricted by the time-to-failure limit of the metallic field line 5 due to electromigration. Moreover, the use of a narrow field line 5 with a high sheet resistance may cause the intensity of the magnetic field 52 to decrease along the field line 5 due to ohmic drop, limiting the number of memory cells 1, 10 being adequately addressed along the field line 5.
In order to minimize the ohmic drop effect along the field line 5, the magnetic memory device can be segmented in sub-arrays (not shown), each sub-array comprising a smaller number of memory cell. This configuration, however, requires an additional driver transistor for every additional field line 5 to drive the current to the appropriate field line 5 for each sub-array. This results in an increased magnetic memory device size and circuit complexity.